Towards accurate FPGA area models for FPGA architecture evaluation

Field Programmable Gate Array (FPGA) devices are integrated circuit chips which can be configured by the end user. FPGA architectures have evolved into heterogeneous System-on-Chips (SoCs) devices in order to meet the diverse market demands. Integrating reconfigurable fabrics in SOCs require an accurate estimation of the layout area of the reconfigurable fabrics in order to properly accommodate early floor-planning. Hence, this work provides an evaluation on the accuracy of the minimum width transistor area models in ranking the actual layout area of FPGA architectures. Both the original VPR area model and the new COFFE area model are compared against the actual layouts with up to 3 metal layers for the various FPGA building blocks. We found that both models have significant variations with respect to the accuracy of their predictions across the building blocks. In particular, the original VPR model overestimates the layout area of larger buffers, full adders and multiplexers by as much as 38% while underestimates the layout area of smaller buffers and multiplexers by as much as 58% for an overall prediction error variation of 96%. The newer COFFE model also significantly overestimates the layout area of full adders by 13% and underestimates the layout area of multiplexers by a maximum of 60% for a prediction error variation of 73%. Such variations are particularly significant considering sensitivity analyses are not routinely performed in FPGA architectural studies. Our results suggest that such analyses are extremely important in studies that employ the minimum width area models so the tolerance of the architectural conclusions against the prediction error variations can be quantified. This work proposes a more accurate active area model to estimate the layout area of FPGA multiplexers by considering diffusion sharing and folding. In addition, we found that comparing to the minimum width transistor area model, the traditional metal area based stick diagrams, in lieu of actual layout, can provide much more accurate layout area estimations. In particular, minimum width transistor area can underestimate the layout area of LUT multiplexers by as much as a factor of 2-3 while stick diagrams can achieve over 85% -95% percent accuracy in layout area estimation. Based on our work, we present correction factors to the commonly used FPGA building blocks, so their actual layout area can be used to achieve a highly accurate ranking of the implementation area of FPGA architectures built upon these layouts.