Subthreshold Frequency Synthesis For Implantable Medical Devices

In this thesis, several novel circuits for use in an ultra-low power integer-n frequency synthesizer operating in the 402 MHz to 405 MHz Medical Implant Communication Service spectrum have been proposed. The proposed designs include a current-reuse quadrature voltage-controlled oscillator, a novel subthreshold source-coupled logic D-latch with clear and preset functionality, a programmable frequency divider and phase/frequency detector based on the aforementioned D-latch, and a modified current-steering charge pump. A design methodology for low-power CMOS oscillators was proposed based on the MOS EKV model and g_m/i_d design methodology. The proposed designs were implemented using IBM CMRF8SF130 nm CMOS technology and simulated using Cadence Spectre. Simulation results for the proposed current-reuse quadrature voltage-controlled oscillator and programmable frequency divider consume 420µW and 200µW respectively from a 0.7 V supply, a significant improvement compared to existing designs. The simulated phase noise of the proposed oscillator is -127.2 dBc/Hz at a 1 MHz offset. Measurement results from a fabricated prototype of the current-reuse quadrature verify the simulation results and serve as a proof-of-concept for the proposed design. The proposed designs were used to implement an integer-n frequency synthesizer and were submitted for fabrication. Simulation results show that the synthesizer consumes 635µW from a 0.7 V supply and has a locking time of 250µs.