Hardware Software Co-Synthesis of Heterogenous Hypercube Architectures for Fault Tolerant Embedded Systems

The hardware-software synthesis of an embedded system's architecture involves the partitioning of a system specification into hardware and software modules so as to meet various non-functional requirements. A designer can specify many non-functional requirements including cost, performance, reliability etc. In this thesis, we present an approach to the hardware-software co-synthesis of embedded systems targeting hypercube topologies. Hypercube topologies provide a flexible and reliable architecture for an embedded device with multiple processing elements. To the best of our knowledge, this is the first time that hypercube topologies have been supported in a co-synthesis algorithm. The co-synthesis approach represented here supports the following features: 1)input in the form of an acrylic periodic task graph with real-time constraints, 2) the pipelining of task graphs, 3) the use of a heterogeneous set of processing elements, 4) Support for fault tolerance through our newly developed group based fault tolerance technique. The co-synthesis algorithm has been applied to two case studies to demonstrate its efficacy.