Frequency calibration of the system clock of passive wireless microsystems

This thesis presents a theoretical and simulated study of frequency calibration of the system clock of passive wireless microsystems. The proposed frequency calibration technique achieves ultra-low power, high fre- quency accuracy, and fast calibration of the frequency of a local oscillator in a passive wireless microsystem using a frequency-locked loop (FLL). A new integrating frequency dif- ference detector (iFDD) that senses the frequency difference between the local oscillator and a reference clock is also proposed. The iFDD is implemented using a switched-capacitor network with two integrating paths. The FLL is composed of a logic-control block for gen- eration of clock signals, the iFDD, and a relaxation voltage-controlled oscillator. A detailed analysis of the characteristics of the iFDD in the time and frequency domains is presented. The loop dynamics of the FLL is also investigated. The proposed FLL is implemented in IBM 0.13-µm, 1.2 V CMOS technology and is validated through simulations using Spectre APS.