Time-mode signal processing and application in ΔΣ ADC design

An all-digitally implemented 1st order and a 2nd order time-mode ΔΣ ADCs are proposed and presented in this dissertation. Each proposed ΔΣ ADC consists of a voltage-to- time integration converter, a seven-stage gated ring oscillator functioning as a 3-bit quantizer, and a 7-stage digital differentiator that provides noise-shaping and frequency feedback. The 2nd order architecture differs from the 1st order by cascading two digital differentiators. The 2nd order design improves noise-shaping characteristic and SNDR. However it does not effectively suppress the harmonic tones due to the non-linear effect of the circuit components. Thus a detailed analysis of the nonlinear characteristics of the modulator is conducted. Designed in IBM 130 nm 1.2 V CMOS technology and with a 100 kHz 100 mV input, the 1st order time-mode ΔΣ ADC exhibits an SNDR of 45.5 dB over 0.4 MHz bandwidth with power dissipation of 1.1mW. In comparison, the 2nd order ADC provides 54.8 dB SNDR, which equivalently offers an ENOB of 8.8 and it consumes 1.45 mW RMS power. The figure- of-merit of the 2nd order time-mode ΔΣ ADC is 407 pJ/step. Since the order of the system cannot be increased by simply cascading more differentiator stages, a time-mode ΔΣ ADC architecture employing a time-mode loop filter is suggested in the last chapter. Several key building blocks including a time amplifier, time register and time adder for implementing such a loop filter are presented. The time amplifier has an input dynamic range of 50ps and provides a gain of 20. The implemented time register has a dynamic range of 5ns and a peak error of 2% over the 5ns full scale. The time adder remains high accuracy as long as the input time difference is no greater than 1:6ns.