Successive Approximation Analog-to-Digital Converters In Time-Mode Signal Processing

The need for Time-Mode Signal processing is discussed. A background for Analog-To-Digital Converters is reviewed. Different approaches and key building blocks of Time Mode Analog-to-Digital conversion are discussed. A new approach for Successive Approximation Register (SAR) Time-to-Digital Converter (TDC) which is called Double Edge SAR TDC is presente. A 4-bit implementation of the Double Edge SAR TDC is done in 65nm TSMC technology and compared against a standard implementation. The new 4-bit design is the Double Edge SAR TDC is able to achieve an ENOB of 3.91 bits and is able to achieve 24% power saving over the classic architecture. The Double Edge SAR TDC is then integrated in a 7-bit two-step Time Domain ADC which was able to achieve an ENOB of 5.312 bits and FOM of 173.5 fJ/conv.