Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

The Network-on-Chip concept is emerging as a promising new method of addressing the communication requirements of complex Systems-on-Chip. However, network design at this level must take into consideration the specific communication protocols of on-chip components. This thesis presents a topology analysis and design method for networks-on-chip based on the transaction-oriented protocols common to on-chip systems. The generated topologies target the latency of critical links in the system, while the analysis method can predict the degree of contention in a system prior to the simulation phase. The proposed topologies are tested using various applications, including an MPEG4 Decoder, and are found to perform the same or better than regular topologies, while using less network resources. The contention prediction method is found to be accurate to within 27% in the worst case scenario.