Maximizing the Logic Capacity of FPGAs for Low-Power Applications

Field Programmable Gate Arrays (FPGAs) are a popular digital platform that can be programmed to implement any digital circuit. Compared to their competitors, FPGAs typically consume higher power, which limits their logic capacity under a given power budget. It is imperative to reduce the power consumption of FPGAs for them to be considered a viable platform for low-power applications. To that end, this thesis investigates techniques to reduce the power consumption of FPGAs. We address both average and peak power consumption of FPGAs. To accurately evaluate the peak power reduction techniques, we considered the transient behaviour of power-constrained sources. In low-power designs, the availability of power consumption data is of absolute importance for power-aware design decisions. To facilitate a quick power estimation at an early stage of design, we developed a static power estimation model. The proposed model estimates the static power of FPGAs with an accuracy of more than 75% across different process technologies. To improve the average power consumption of single-context FPGAs, we investigated the voltage downscaling technique. The look-up-tables in conventional NMOS-Pass-Transistor (NPT)-based FPGAs are vulnerable at low voltage and can cause malfunctioning. By modifying the look-up-tables, we were able to operate NPT-based FPGAs at 0.2—0.5V lower than the nominal voltage. By operating at lower voltages, we achieved 20-74% lower power-delayproduct and 4.5-8.5 times higher logic capacity in the limited power budget.