Layout Design of a Sample Rate Converter for an LTE Receiver

In the world of complicated electronics, digital synthesis with an integrated application of a complex chip design is usually bundled into large EDA software systems like Cadence or Synopsys. As commercial electronics designers need to maintain cutting edge performance quality, these huge commercial toolchains get more and more expensive, and have largely priced themselves out of all but the established integrated circuit creators. This leaves a huge gap where Startup companies and small businesses owners cannot afford to work on any sort of integrated circuit design. The digital synthesis algorithms are all tied up in closed source software tools, and development process is driven by several EDA software makers.

ASIC Design Flow requires many EDA tools and industry uses some of the advanced EDA tools. For expanding your knowledge on these tools and the design flow opensource EDA tools can be used and applied to your design.

We selected an already exist sample rate converter circuit in MATLAB Simulink environment to feed our free VLSI system tool called Qflow tools that works in Linux operating system.