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Design and implementation of programmable pipelined FIR filter in FPGA

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posted on 2021-06-08, 11:47 authored by Ganendran Narasingavel

Since the introduction of DSP blocks in commercial FPGAs such as Altera Stratix II and Xilinx Virtex II, DSP applications are increasingly being implemented on FPGAs. This project imprlements a pipelined digital FIR filter with programmable coefficients in an Altera Cyclone II FPGA. An automated test system is also constructed to verify the design. The project places equal emphasis on implementing a programmable FIR as well as building an automated test system, Also, we will evaluate the practicality of the design by comparing the design to the FIR IP core provided by Altera.





Master of Engineering


Electrical and Computer Engineering

Granting Institution

Ryerson University

LAC Thesis Type

Thesis Project

Thesis Advisor

Andy Gean Ye