Design and implementation of portable and configurable RISC processor architecture

This project presents the configurable microprocessor design based on the MIPS architecture. The level of configurability includes a choice of the pipe lined or unpipelined architecture, number of pipeline stages, data path bit-width, instruction subsetting, program and data memory size. The microprocessor design flow is supported by the set of standard and custom software tools. The wide spectrum of the microprocessor configurations provides an opportunity to optimize hardware for the specific application. The HDL design of the microprocessor is independent of the hardware platform. The portability of the design was verified on the competitive FPGA platforms and ASIC. The selected microprocessor configuration running the test application was successfully implemented and verified on the FPGA development board. The obtained implementation results were compared to the existing commercial and research microprocessors and critical advantages of the presented design were outlined.