As the multi-core computing era continues to progress, the need to increase single-
thread performance, throughput, and seemingly adapt to thread-level parallelism
(TLP) remain important issues. Though the number of cores on each processor
continues to increase, expected performance gains have lagged. Accordingly, com-
puting systems often include Simultaneously Multi-Threaded (SMT) processors as
a compromise between sequential and parallel performance on a single core. These
processors effectively improve the throughput and utilization of a core, however often
at the expense of single-thread performance as threads per core scale. Accordingly,
applications which require higher single-thread performance must often resort to
single-thread core multi-processor systems which incur additional area overhead and
power dissipation. In attempts to improve single- and multi-thread core efficiency,
this work introduces the concept of a Configurable Simultaneously Single-Threaded
(Multi-)Engine Processor (ConSSTEP). ConSSTEP is a nuanced approach to multi-
threaded processors, achieving performance gains and energy efficiency by invoking
low overhead reconfigurable properties with full software compatibility. Experimen-
tal results demonstrate that ConSSTEP is able to increase single-thread Instruc-
tions Per Cycle (IPC) up to 1.39x and 2.4x for 2-thread and 4-thread workloads,
respectively, improving throughput and providing up to 2x energy efficiency when
compared to a conventional SMT processor.