Khan_Nawreen_Rashid.pdf (3.47 MB)
Download file

Circuits and architectures for high frequency synthesizer in CMOS

Download (3.47 MB)
thesis
posted on 2021-06-08, 12:19 authored by Nawreen Rashid Khan
This thesis proposes a novel architecture for high frequency synthesizer design focusing mainly on the 60 GHz frequency range. It consists of a PLL cascaded to an ILO. In order to generate narrow pulses and to relax the multiplication ration of the ILO, a DLL with a pulse generator is used. Passive delay line stacked on top of LC VCO is used for power efficiency and replica-biasing technique of frequency tracking is used for increasing the locking range of ILO. The synthesizer operates at 50 GHz with a phase noise of -98, -117 and -128 dBc/Hz at 1 MHz, 10 MHz and 40 MHz respectively. The total power consumed by the frequency synthesizer from 1.2 V supply is 57 mW. To have channel selection capability, fractional PLL may be used. A novel fractional PLL architecture is also proposed which de-couples the residual jitter from the PLL bandwidth.

History

Language

eng

Degree

Master of Applied Science

Program

Electrical and Computer Engineering

Granting Institution

Ryerson University

LAC Thesis Type

Thesis

Thesis Advisor

Xijia Gu