Cache filtering algorithm for least frequently used data with accurate memory simulation

We propose a cache filtering algorithm to improve processor performance using a small buffer inside the processor and an algorithm to filter least frequently used accesses from Ll and L2 caches. The algorithm uses simple DRAM fast-page accessing mode to identity accesses that are not previously accessed or not frequently used and keep them out of the cache system and store them in small buffer. We have also added a realistic page interleaved DDR3 memory simulation model to the SimpleScalar simulator. This model supports any processor and memory clock speeds, different sets of memory latencies, various configurations of memory banks and channels. Results show that the filtering algorithm could improve· performance of some applications compared to the same system that does not use the filtering algorithm