Area-delay driven library-free synthesis

Current logic synthesis tools rely on pre-defined cell libraries to assemble an arbitrary circuit to perform a needed function. The efficiency of the synthesized circuit relies on the quality and size of the library used in terms of circuit area and critical path delay. It has been shown that in a process supporting five serial NMOS and PMOS transistors, 425803 unique logic gates may be constructed. Clearly this is beyond what is currently available in standard cell libraries. A richer cell library allows the technology mapper more freedom to better select matches to reduce area, delay and power consumption. This thesis proposes novel algorithms for mapping an input netlist to a library of virtual cells by minimizing logical effort delay, and gate input capacitance to select an architecture which minimizes the design areadelay. An average 69.43% reduction in transistor count, 53.33% reduction in circuit area, with a 3.76% increase in delay has been realized compared to results obtained from Synopsys Design Compiler with high map effort for delay minimization.