Toronto Metropolitan University
Javaheri_Mohammad_Reza_Samadpour.pdf (3.36 MB)

An arithmetic approach to the analysis of multiple faults verification and synthesis at switch-level

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posted on 2021-05-22, 14:20 authored by Mohammad Reza Samadpour Javaheri
Switch-level modeling and simulation has become an important method of predicting the behaviour of CMOS circuits under the presence of faults. Many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength can be reliably modeled using this technique. This paper presents an algorithm for modeling directional and bi-directional CMOS circuits with an arithmetic solution for circuit verification and fault synthesis. This new approach is capable of simulating multiple fault injection into the circuit and speeds up switch-level simulation. Other advantages of this algorithm are its application in the mapping of single and multiple faults from switch level to gate level and the ability to function as a multi-level model. Multiple faults can be of the same or different types. Experimental results using Cadence tools show that the algorithm is successful and reliable for CMOS technology.





  • Master of Applied Science


  • Electrical and Computer Engineering

Granting Institution

Ryerson University

LAC Thesis Type

  • Thesis

Thesis Advisor

Reza Sedaghat