A hardware based technique to reduce the timing complexity of number factoring problem

Most digital circuits which have been developed to implement algorithms, can benefit from an increase in clock speed, but do not completely map the problem to all available silicon resources. We have introduced a hardware based scheme capable of effectively using technology, specifically the increase in silicon area, to improve the computational time of complicated applications. In this thesis, we applied this scheme to solve the factoring problem, which requires exponential time (with respect to the number of bits in n) in conventional computers and could be only solved in polynomial time with quantum computers. The scheme successfully mapped the problem to most of the silicon area of Altera Stratix FPGA. The results show that the scheme is capable of reducing the time complexity to a polynomial rate with respect to the number of bits of the number n. The results also show an exponential rate of use for silicon with respect to the number of bits of n. Our analysis shows that the new scheme is scalable with technology speed and available space, could be applied to other applications to solve the performance limitations of conventional systems.