Toronto Metropolitan University
Browse

3.3V Transmitter Using 1.8V Transistors In A Cascode Configuration

Download (2.06 MB)
thesis
posted on 2021-05-24, 11:00 authored by Marcs Ng
A voltage-mode transmitter using a 1.8V-to-3.3V levelshifter and cascoded output buffer is proposed. 1.8V TSMC 65nm transistors are used. The design is targeted to meet JEDEC Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits DC Specifications as well as an AC transmission rate of 200 MHz on a 30 cm 50Ω board trace terminated with a 4 pF capacitive load. Overstress voltages will not be exceeded in order to avoid device failure due to breaching Gate Oxide Integrity, Hot Carrier Injection, or Negative Bias Temperature Instability.

History

Language

English

Degree

  • Master of Engineering

Program

  • Electrical and Computer Engineering

Granting Institution

Ryerson University

LAC Thesis Type

  • Thesis

Year

2013

Usage metrics

    Electrical and Computer Engineering (Theses)

    Exports

    RefWorks
    BibTeX
    Ref. manager
    Endnote
    DataCite
    NLM
    DC