Bandwidth amplification using pre-clocking

Technologies are generally described herein for bandwidth amplification using a pre-clock signal to latch data at a latch in an input register of a sender section while passing the data through a multiplexer of the sender section in a serial manner. In some configurations, pre-clocking the multiplexer can allow for parallel operations to occur within the sender section, thus hiding or reducing the effects of certain serialization delays associated with the multiplexer. Furthermore, the pre-clocking of the multiplexer, in some configurations, hides or reduces the register latch hold and setup delays. A method may create three levels of parallelization of latencies between a sender circuit, a serialization circuit, and a receiver circuit by overlapping them at same time.