Cost Effective Reconfigurable Architecture for Stream Processing Applications

This paper presents an approach for development of costeffective custom video / image processing systems. The approach utilizes the concept of temporal partitioning of resources in the partially reconfigurable FPGA devices. Paper proposes architecture of the multi-mode video-stream processor with cyclically reconfigurable structure. The cost-effectiveness of the proposed approach has been analyzed on the basis of experiments conducted on Multi-mode Adaptive Reconfigurable System (MARS) platform that was developed for that purpose. The video-processing cores associated with stereo-vision algorithms have been developed, tested and analyzed. The experiments have shown that the cost-effectiveness of the systems based on proposed approach can be better than the traditional approaches based on large statically configured FPGAs.