Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture

In this paper we present a concept of the self-assembling micro-architectures of Application Specific Virtual Processors for data-stream processing. The procedure for micro-architecture assembling is developed for Xilinx "Virtex" FPGA devices. It is shown that proposed approach allows a minimization of system resources for multi-task data-stream workload and gives ability for self-restoration of processing micro-architectures when hardware fault occurs. This Paper presents a description of system level architecture of run-time re-configurable multi-stream parallel processor for video applications and results gained on the prototype.