Toronto Metropolitan University
Browse

An 8-bit digital-to-time converter with pre-skewing and time interpolation

Download (2.72 MB)
journal contribution
posted on 2022-10-14, 13:54 authored by Daniel Junehee Lee, Fei Yuan, Gul KhanGul Khan, Yushi Zhou

This study presents an 8‐bit delay line digital‐to‐time converter (DTC) with pre‐skewing and digital time interpolation. Pre‐skewing that lowers the per‐stage‐delay of delay lines beyond that set by the chosen technology is investigated. A cascode tri‐state inverter is proposed to improve the isolation between the input and output of interpolation cells so as to improve the linearity of the time interpolator. Design considerations that critically affect the linearity of the DTC are examined in detail. The impact of the slope of the inputs of the time interpolator on the latency and linearity of the interpolator is analysed and the maximum slope of the input of interpolators yielding the minimum latency without sacrificing linearity, is obtained. The timing errors of DTC are investigated and the considerations of the layout of the DTC are examined. The DTC is designed in a TSMC 65 nm 1.0 V CMOS technology and analysed using Spectre with BSIM3V3 device models. Post‐layout simulation results show the DTC offers 3.6 ps resolution, 580 MS/s conversion rate, and consumes 383 μW.

History

Language

eng

Usage metrics

    Computer Engineering

    Licence

    Exports

    RefWorks
    BibTeX
    Ref. manager
    Endnote
    DataCite
    NLM
    DC