Signature Testing of Analog-To-Digital Converters

When testing an analog-to-digital converter (ADC) by automatic test equipment (ATE), the latter is capable of performing extensive processing of output responses of the ADC. This allows detection of virtually any fault. However, the cost of ATE is quite high. As well, the external bandwidth of ATE is normally lower than the internal bandwidth of the ADC being tested, which makes it difficult to accomplish at-speed testing. It is important, therefore, to embed test hardware into ADC itself. The methods employed at ATE are complex and inconvenient for built-in realization. More advantageous are the methods exploiting accumulation of output responses. The size of the accumulator depends on the number of responses. In order to achieve greater fault coverage, this number is kept large, complicating the implementation. On the other hand, signature analysis used in digital systems testing is well suited for compaction of “lengthy” responses, and it is characterized by small hardware overhead and low aliasing probability. In this work, we apply signature analysis principle for compaction of output responses of an ADC. The permissible tolerance bounds for a fault-free ADC are determined and the aliasing rate is estimated. Examples are given.