Self-Restoration as SEU Protection Mechanism for Re-Configurable On-Board Computing Platform

The following paper presents multi-level protection mechanism for the digital processing circuits, based on partially re-configurable FPGA devices and runtime reconfiguration of processing architectures in the FPGA device. This approach assumes that if a hardware fault occurs in one of task processors, it can be restored without interruption of any computing processes in the rest of FPGA circuitry. The novel procedures of function restoration with and without performance degradation are proposed. These procedures allow automatic restoration of Application Specific Virtual Processors inside the FPGA device with minimization of performance degradation when a fault occurs. Implementation of this method can dramatically increase lifetime of the onboard computing platform and at the same time reduce restoration time period.